1. Field of the Invention
The present invention relates generally to clock distribution systems in integrated circuits. It particularly relates to a clock distribution system using clock gating to control power.
2. Background
In modern integrated circuits, such as computer processors, it is common to use clock gating as a power control technique. A driving clock signal energizes components of a circuit. Data signals determine the circuit""s response and may generate still other data for use by other circuits. When a circuit is not used, however, it is common to disable the clock signal by stopping the clock signal entirely or substantially reducing its clock activity (frequency) as it is input to the circuit. Consequently, the circuit components are substantially de-energized and power consumption is reduced. xe2x80x9cClock gatingxe2x80x9d refers generally to techniques to manage the enabling and disabling of clock signals to individual components to conserve power.
Clock gating circuits typically are integrated as part of a clock distribution network. Often, the distribution network is organized according to a tree structure such as the clock distribution network 100 shown in FIG. 1. A clock signal 101, generated by clock generator 102, propagates from a root level 106 (level 1 ) of the network 100 (tree) including a plurality of branches (106-1 to 106-N) to one or more lower branch levels 108 (level 2) including a further plurality of branches (108-1 to 108-N). Clock gating logic circuits 104 are provided along the branches where each gating circuit 104 receives a local clock gating condition (enabling/disabling) signal 110 and the propagating clock signal as inputs. Each gating logic circuit 104, located along a branch, may block (disable or slow) a regular clock signal from propagating further along the respective branch if the local clock gating conditions trigger clock gating.
When the branches themselves branch when going from root level 106 (level 1) to lower branch level 108 (level 2), gating logic circuits 104 are provided again on each further branch (sub-branch), again to block (or slow) propagation of the clock signal. This technique may be repeated for as many branches as are present in the clock distribution network until the clock is input to a local circuit 112. The clock signal may traverse multiple gating circuits as it propagates from the root node to a terminal branch of the tree. However, as shown in this technique, the enabling signal for the local clock gating condition 110 must be redundantly input at each branch level, and clock gating triggered at an upper branch level (e.g., 106xe2x80x94level 1) will disable (or slow) the clock signal at all lower branch-levels (e.g., 108xe2x80x94level 2).
Furthermore, now that clock frequencies (especially in high-performance processor systems) are meeting and exceeding the multiple GHz (giga-hertz) frequency level, disadvantages with conventional clock gating schemes are becoming apparent. Ideally, rising and falling edges of a driving clock signal should arrive at each local circuit at exactly the same time. An optimal clock distribution scheme should eliminate clock skew effect associated with the clock signal arrival at the local circuits. Skew may be caused by a plurality of factors including, but not limited to, uneven clock load (glitches) in the clock distribution network, a high number of circuits in the clock distribution network, wiring distance, repeater usage, or other factors. Also, the varying number of gating circuits that are traversed from the root node to each of the local circuits may add skew and other spurious effects. Furthermore, clock frequencies operating at the multiple GHz range provide a very short setup time (for clock gating) due to the limited (reduced) duty cycle of a very fast clock. Accordingly, a new clock distribution scheme is needed to reduce (or eliminate) clock glitch and to provide a minimum physical distance between the clock gating control circuitry and the local circuit to be clock-gated.